1. Field of the Invention
The present invention generally relates to standards of measurement (metrics) for characterizing features of electrical circuits, and more particularly to a method and system for establishing delay and slew metrics for resistive-capacitive (RC) networks, such as those in an integrated circuit.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cells types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. An electronic design automation (EDA) system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.), and translates this high level design language description into netlists of various levels of abstraction. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the sub-micron regime, interconnect delays increasingly dominate gate delays. Consequently, physical design optimization tools such as floorplanning, placement, and routing are becoming more “timing-driven” than the previous generation of tools. For such a tool to be effective, it must be able to efficiently compute interconnect delay since several million delay calculations are required to optimize a design.
In certain types of circuits, delays exist based on circuit topology and circuit components. Delays are particularly acute in circuits having resistive and capacitive elements, or RC circuits, as they are called in the art. A schematic diagram showing a generalized RC circuit is shown in FIG. 1. Circuit designers continually search for efficient techniques for accurate estimation of these delays, while determining the particular circuit's response to a load. In particular, circuit designers want to be able to calculate reliable delay information when designing the circuit. To this end, several prior art metrics (i.e., computational methods) have been developed.
The Elmore delay metric, which calculates the first moment of the impulse response, is the most widely applied and simplest interconnect delay metric that still captures some amount of metal resistance effects. The Elmore metric provides an upper bound on delay given any input waveform because the RC circuit impulse response is unimodal and positively skewed. The Elmore delay metric is commonly utilized for performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing in part and global routing. The widespread use of the Elmore delay metric is due to its closed form expression, fast computation speed, and fidelity with respect to simulation. Closed form delay equations, such as Elmore delay metric, are certainly preferable due to both efficiency and ease of implementation, as long as they are sufficiently accurate. Despite its wide usage, the Elmore delay metric is known to be extremely inaccurate at times because it ignores the resistive shielding of downstream capacitance.
Several of the other traditional metrics are known to be more accurate but are somewhat CPU intensive or difficult to implement. For example, moment matching via asymptotic waveform evaluation (AWE, implemented in an interconnect analysis called RICE ) is very accurate but computationally expensive for use within a tight optimization loop. Two-pole variants of AWE are considerably faster and recognized to be more accurate than the Elmore delay metric, but are still relatively expensive, as nonlinear solution methods such as Newton-Raphson iterations need to be run to solve the transcendental equation. The metric commonly referred to as PRIMO fits the moments of the impulse response to probability density functions by utilizing a table lookup operation. The h-gamma metric (which subsumes PRIMO) avoids time-shifting the distribution functions and matches the moments to the circuit's homogenous response. The gamma solution also requires a lookup table which is not trivial to build. The scaled Elmore delay metric shifts the Elmore approximation and the error, but does not change the relative delay error problem. Another closed form RC delay metric is described in U.S. Pat. No. 6,434,729, which calculates two moments of impulse response for an RC circuit, and computes a delay value for each node of the circuit based on these two moments. Each node is analyzed to determine if the delay at the given node is at a desired optimization condition.
In almost all of these works, the delay metric assumes a step excitation. In any practical application, the interconnect is driven by a non-linear device and the driving-point waveform is not a step. It is common practice for conventional timing analyzers to replace the non-linear driver by an ideal voltage source generating a saturated ramp signal that has the same 10-90 transition time as the original waveform. Thus, any practical delay metric should be able to handle non-zero input slew (slew generally refers to the signal transition time). The H-gamma method adds a third dimension to the two-dimensional lookup table used for computing step delay. While being accurate, this method requires a carefully constructed table which is made harder by the fact that input slews can vary over a wide range, especially during the initial stages of design. For methods which compute delay directly as a function of moments, either through a lookup-table or an explicit formula, a form of “moment massaging” (PRIMO) is used to handle non-step inputs. The impulse response moments are modified to account for the non-zero input slews and these modified moments are used in the original step formula. The advantage of this approach is that the delay metric remains a closed-form formula even for ramp inputs. However, the formula is only valid for very fast input slews and has large errors for even moderately slow inputs.
In light of the inherent drawbacks with using the various metrics currently available for measuring delays and slew in ramp inputs, it would be desirable to devise an improved method for extending any delay metric derived for a step input into a delay metric for a ramp input for RC trees that is valid over all input slews, to provide greater reliability and accuracy in computing delays in a RC circuit of any topology. It would be further advantageous if the method had such improved effectiveness while not adding computational complexity. It would also be desirable to provide closed form formulae for delay and slew metrics which are more accurate and allow more efficient circuit timing and optimization.